--
-- VHDL Architecture vga_lib.blank_sync.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:26:56 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY blank_sync IS
   PORT( 
      vga_blank_n : OUT    std_logic;
      vblank      : IN     std_logic;
      hblank      : IN     std_logic
   );

-- Declarations

END blank_sync ;

--
ARCHITECTURE arch OF blank_sync IS
BEGIN
  vga_blank_n <=  hblank nor vblank;
END ARCHITECTURE arch;

